“We can create this heterogeneous integration that allows us to put the chips into a system and input completely different kinds of chips, whether it’s analog, mixed signal, digital, or even sensors,” said Yin Chang, senior vice president at ASE, in a recent presentation. And on the design side, it requires complex partitioning, keeping in mind a whole slew of possible physical/proximity effects, often in multiple dimensions - along the x, y, and z axes, as well as over time. Sometimes it requires more or different equipment. While that could change with the introduction of standard interfaces and chiplets, the current approaches put pressure on equipment makers, foundries, and packaging houses to build flexibility into their products and processes, and it’s not always feasible. In fact, there are so many possible configurations that even finding overlaps between devices to simplify manufacturing and test is difficult at this point. Scaling of digital logic already is out of sync with other technologies, such as memory, and analog gains nothing by scaling it to a smaller geometry. Packaging adds flexibility and options for specialization that are not feasible on a planar device, even for those companies with the deepest pockets. Still, this presents a tricky balance between mass production and customization. In addition, we will need time-sensitive data, and that data has to be actionable.” “Standards will be required to achieve high volume and to have a high impact on failure. “Everyone in the ecosystem now has a say in building a system, and each one has to play their part,” said Kent Stahn, package design engineer at Synopsys. That will have to change at some point in order to bring these designs into the mainstream and to connect the pieces across the supply chain. Every company is charting its own course to some extent.”

So the classic mantra of the semiconductor industry, where everything is standardized and billions of chips are made the same way, is breaking apart in the advanced packaging world. “Within those, there are various different approaches, like TSMC’s CoWoS.

“Different companies are taking different approaches, whether it’s a fan-in or fan-out,” said Subodh Kulkarni, CEO of CyberOptics. Unlike in the past, when a design was perfected for 1 billion units, some of these devices are being rolled out in much more limited quantities, and all of this is happening under much tighter time constraints. It’s likely that not all of them will age evenly. That requires a deep understanding of all the individual parts, as well as the interconnects and the packaging materials, in order to function properly throughout that lifetime. Others may only be expected to last a few years. Some of these packages are being developed for automotive, mil/aero, and industrial applications, where lifetimes can be as long as 25 years. Because many of these designs are customized for a particular application or market segment, there are few, if any, off-the-shelf models for design, aging, or manufacturing (PDKs). This is particularly problematic for inspection, metrology, and test, because not all of the pieces of a unique design may be accessible. While some problems are simpler, such as designing a power delivery network or floor-planning for heat or data flow, the integration of multiple chips can cause a wide range of interactions - some of which may only show up in one particular implementation. However, all of this flexibility, integration, and specialization comes at a cost: And analog sensors and other components that were developed at, or optimized for, an established process node can be integrated with other components developed at new or older nodes. Those approaches also have made it easier to integrate various types and amounts of memories and processing elements into a package. Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore’s Law and the ITRS roadmap created a semi-standardized path forward for the chip industry.ĭifferent advanced packaging options - system-in-package, fan-outs, 2.5D, 3D-IC - have added the flexibility needed to target specific applications, markets, and use cases.

Xsection of ic chip